Analog-Precision Board

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Filename	Downloads	Message	Posted
CLK-ADC.bmp	1,071	Buffered Output from the clock buffer chip feeding the ADC	November 19, 2020, 08:25:22 PM
Jtest-Coax-DPLL=13.png	1,075	DPLL BW=13	March 09, 2021, 11:47:50 PM
CLK-CPLD.bmp	1,076	Buffered Output from the clock buffer chip feeding the timing logic !	November 19, 2020, 08:27:15 PM
Jtest-Coax-DPLL=12.png	1,076	DPLL BW=12	March 09, 2021, 11:47:11 PM
P1050165.JPG	1,077	5: Apodizing, fast roll-off, linear phase filter	March 08, 2021, 11:47:34 PM
Filter-5.png	1,077	5: Apodizing, fast roll-off, linear phase filter	March 08, 2021, 11:47:34 PM
Jtest-Coax-DPLL=3x.png	1,078	DPLL BW = 3	March 09, 2021, 11:39:00 PM
Filter-2.png	1,079	2: Slow roll-off, linear phase filter	March 08, 2021, 11:46:08 PM
P1050166.JPG	1,080	6: Hybrid, fast roll-off, minimum phase filter	March 08, 2021, 11:47:53 PM
Filter-6.png	1,081	6: Hybrid, fast roll-off, minimum phase filter	March 08, 2021, 11:47:53 PM
P1050107.JPG	1,083	Clock Fidelity Test	November 19, 2020, 07:02:18 PM
P1050163.JPG	1,085	3: Fast roll-off, minimum phase filter	March 08, 2021, 11:46:36 PM
Filter-7.png	1,086	7: Brickwall filter	March 08, 2021, 11:48:11 PM
P1050164.JPG	1,088	4: Slow roll-off, minimum phase filter	March 08, 2021, 11:47:04 PM
P1050162.JPG	1,089	2: Slow roll-off, linear phase filter	March 08, 2021, 11:46:08 PM