Introduction:In this exercise we continue on with the jitter tests using the J-test methodology outlined in our original
jitter test thread but this time we want to see how the jitter performance varies as we change the DAC Digital PLL bandwidth. The ES9038PRO DAC has 15 different settings for Digital PLL bandwidth but obviously the tighter the bandwidth the better the jitter performance but this comes at the expense of the DAC being able to lock onto an asynchronous signal with inherent jitter so there is a trade-off between bandwidth and jitter tolerance.
Test Methodology:There are a variety ways of measuring jitter but the single single RMS or peak jitter metric is not very revealing since it does not reveal the nature of the jitter, so a more detailed analysis such as the J-test method is used to test the susceptibility and tolerance of the device under test. The J-test methodology is described on the ASR forum
J-test methodology 1 and
J-test methodology 2Test ResultsConclusion:Below the DPLL BW setting of 5 there doesn't seem to be any more improvement in jitter to be had so it seems like this setting is the best compromise between jitter performance and PLL bandwidth.
