Author Topic: Clock Fidelity Test  (Read 88 times)

David Samborsky

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Clock Fidelity Test
« on: November 19, 2020, 08:02:18 AM »
Test Methodology:

In these tests we are using a wide bandwidth digital scope to view the 49.152MHz master clock waveform at various points in the clock network. It is impossible to make proper measurements of a clock source unless you use a scope with a suitable bandwidth that can at least capture the 21st harmonic of the fundamental frequency of the clock frequency which means a scope with at least a 1GHz bandwidth. Not only that you need to use a probe with an equivalent or greater bandwidth to the scope and preferably an active probe to minimize loading.

To avoid loading down the device under test we use an active probe (Tek P6204) with at least 1GHz bandwidth along with the shortest ground connection to minimize loop inductance in the probe which would manifest itself as ringing in the waveform. We used a Tektronix TDS784A DSO scope with a 1GHz bandwidth and real time sampling rate of 4Gs/s as well as a 10Gs/s equivalent time sampling rate for our measurements. For the expanded scale measurement the scope was set to an equivalent sampling rate of 100 Gs/s. What we are looking for is minimum ringing and overshoot without any kinks in the clock transition interval.

Test Results:


Conclusion:

As one can see from the scope shots below that in all cases the clock wave-forms are clean and stable and show minimum overshoot which means that the clock outputs are properly matched to the board traces in order to minimize transmission line effects and reflections.



Tektronix P6204 Low Capacitance Active Probe with 1GHz bandwidth



Active Probe applied to clock circuit using the shortest possible ground connection for minimum induced ringing and overshoot ;)





« Last Edit: November 20, 2020, 06:07:24 AM by David Samborsky »
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David Samborsky

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[b]Frequency Measurement[/b]
« Reply #1 on: November 19, 2020, 09:19:11 AM »
Frequency is pretty much spot on !!



« Last Edit: November 19, 2020, 09:38:23 AM by David Samborsky »
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David Samborsky

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Raw Output from the master clock oscillator
« Reply #2 on: November 19, 2020, 09:23:10 AM »
Very well defined with no overshoot and smooth crossover transition !

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David Samborsky

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Buffered Output from the clock buffer chip feeding the DAC
« Reply #3 on: November 19, 2020, 09:24:17 AM »
As smooth as ;)

« Last Edit: November 19, 2020, 09:30:06 AM by David Samborsky »
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David Samborsky

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Buffered Output from the clock buffer chip feeding the ADC
« Reply #4 on: November 19, 2020, 09:25:22 AM »
Minimal overshoot and ringing with a well defined transition period !

« Last Edit: November 19, 2020, 09:29:42 AM by David Samborsky »
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David Samborsky

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Buffered Output from the clock buffer chip feeding the timing logic !
« Reply #5 on: November 19, 2020, 09:27:15 AM »
Minimal overshoot and ringing with a well defined transition period !



Expanded scale with equivalent time sampling rate of 100 Gs/s !

« Last Edit: November 19, 2020, 09:29:21 AM by David Samborsky »
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